[PATCH net-next v4 5/6] r8169: fix RTL8116af can not enter s0idle and c10
From: javen <hidden>
Date: 2026-07-03 09:25:29
Also in:
lkml
Subsystem:
8169 10/100/1000 gigabit ethernet driver, networking drivers, the rest · Maintainers:
Heiner Kallweit, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
From: Javen Xu <redacted> RTL8116AF is a multi-function device. Functions 2 to 7 are hidden from the PCI core and return an all-ones response when their vendor ID is read, so they are not enumerated as normal PCI functions. However, these hidden functions can still affect platform power management. If they are left in D0 or keep ASPM disabled, the platform may fail to enter the low-power s0ix state and the CPU package may fail to enter Package C10. Put functions 2 to 7 into D3hot and enable ASPM on their PCIe link control register. Since these functions are hidden, access their configuration space through pci_bus_read_config_dword() / pci_bus_write_config_dword() using the same slot and the target function numbers. Ignore functions that return a PCI error response when reading their configuration space. Signed-off-by: Javen Xu <redacted> --- Changes in v2: - no changes Changes in v3: - no changes Changes in v4: - add gate for rtl_lowpower_hidden_functions, only for RTL8116af --- drivers/net/ethernet/realtek/r8169_main.c | 57 ++++++++++++++++++----- 1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 635131c51db9..0dd805f0d613 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c@@ -97,17 +97,20 @@ #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) -#define OCP_SDS_ADDR_REG 0xEB10 -#define OCP_SDS_CMD_REG 0xEB0E -#define OCP_SDS_DATA_REG 0xEB14 -#define SDS_CMD_READ 0x0001 -#define RTL_SDS_C22_BASE 0x40 -#define RTL_PKG_DETECT 0xdc00 -#define RTL_PKG_DETECT_MASK 0x0078 -#define RTL_PKG_DETECT_8116AF 0x0030 -#define RTL_INT_HW_ID 0xd006 -#define RTL_INT_HW_ID_MASK 0x00ff -#define RTL_INT_HW_ID_8116AF 0x0000 +#define OCP_SDS_ADDR_REG 0xEB10 +#define OCP_SDS_CMD_REG 0xEB0E +#define OCP_SDS_DATA_REG 0xEB14 +#define SDS_CMD_READ 0x0001 +#define RTL_SDS_C22_BASE 0x40 +#define RTL_PKG_DETECT 0xdc00 +#define RTL_PKG_DETECT_MASK 0x0078 +#define RTL_PKG_DETECT_8116AF 0x0030 +#define RTL_INT_HW_ID 0xd006 +#define RTL_INT_HW_ID_MASK 0x00ff +#define RTL_INT_HW_ID_8116AF 0x0000 +#define RTL8116AF_FUNC_PM_CSR 0x80 +#define RTL8116AF_FUNC_EXP_LNKCTL 0x44 +#define RTL_PM_D3HOT GENMASK(1, 0) static const struct rtl_chip_info { u32 mask;
@@ -3779,6 +3782,35 @@ static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); } +static void rtl_lowpower_hidden_functions(struct pci_dev *pdev) +{ + unsigned int slot = PCI_SLOT(pdev->devfn); + struct pci_bus *bus = pdev->bus; + unsigned int devfn; + int func; + int ret; + u32 val; + + for (func = 2; func < 8; func++) { + devfn = PCI_DEVFN(slot, func); + + ret = pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, &val); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val &= ~PCI_PM_CTRL_PME_STATUS; + val &= ~(PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_PME_ENABLE); + val |= (RTL_PM_D3HOT | PCI_PM_CTRL_PME_ENABLE); + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, val); + } + + ret = pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL, &val); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val &= ~((PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16); + val |= PCI_EXP_LNKCTL_ASPMC; + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL, val); + } + } +} + static void rtl_hw_start_8117(struct rtl8169_private *tp) { static const struct ephy_info e_info_8117[] = {
@@ -3835,6 +3867,9 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp) r8168_mac_ocp_write(tp, 0xc094, 0x0000); r8168_mac_ocp_write(tp, 0xc09e, 0x0000); + if (rtl_is_8116af(tp)) + rtl_lowpower_hidden_functions(tp->pci_dev); + /* firmware is for MAC only */ r8169_apply_firmware(tp); }
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2.43.0