[PATCH net-next 8/8] arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH) interface
From: Biju <hidden>
Date: 2026-01-28 12:59:02
Also in:
linux-devicetree, linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
From: Biju Das <biju.das.jz@bp.renesas.com> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3L SMARC EVK. The eth1, pincontrol definitions and hotplug support will be added later. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index 7c21afaee9bc..f52af01a7eff 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi@@ -8,6 +8,10 @@ / { compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; + aliases { + ethernet0 = ð0; + }; + memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */
@@ -15,6 +19,37 @@ memory@48000000 { }; }; +ð0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +ð0_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; + +&mdio0 { + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +};
--
2.43.0