[PATCH net-next 0/8] Add support for Renesas RZ/G3L GBETH

From: Biju Das <biju.das.jz@bp.renesas.com>

The Renesas RZ/G3L GBETH IP uses Synopsys DesignWare MAC version 5.30
compared to other Renesas SoC such as RZ/V2H that use MAC version 5.20.

The RZ/G3L GBETH requires an extra clock compared to RZ/G3E and has pps
interrupts. Document the Renesas RZ/G3L GBETH IP in bindings and enable
the Gigabit Ethernet Interface (GBETH0) populated on the RZ/G3L SMARC
EVK. The eth1, pincontrol definitions and hotplug support will be added
later.

Biju Das (8):
  dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L SoC
  net: stmmac: dwmac-renesas-gbeth: Add support for RZ/G3L SoC
  clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate()
  clk: renesas: rzg2l: Add support for enabling PLLs
  clk: renesas: r8a08g046: Add support for PLL6 clk
  clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs
  arm64: dts: renesas: r9a08g046: Add GBETH nodes
  arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH) interface

 .../bindings/net/renesas,rzv2h-gbeth.yaml     |  77 +++++-
 .../devicetree/bindings/net/snps,dwmac.yaml   |   3 +
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 237 ++++++++++++++++++
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi     |  35 +++
 drivers/clk/renesas/r9a08g046-cpg.c           | 120 +++++++++
 drivers/clk/renesas/rzg2l-cpg.c               |  70 +++++-
 drivers/clk/renesas/rzg2l-cpg.h               |  10 +
 .../stmicro/stmmac/dwmac-renesas-gbeth.c      |   1 +
 8 files changed, 539 insertions(+), 14 deletions(-)

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2.43.0