Re: [PATCH v6 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
From: Stephen Boyd <sboyd@kernel.org>
Date: 2025-09-21 16:53:44
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Quoting Laura Nao (2025-09-15 08:19:28)
On MT8196, some clocks use one register for parent selection and gating, and a separate register for frequency division. Since composite clocks can combine a mux, divider, and gate in a single entity, add a macro to simplify registration of such clocks by combining parent selection, frequency scaling, and enable control into one definition. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Laura Nao <redacted> ---
Applied to clk-next