Re: [PATCH v6 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control
From: Stephen Boyd <sboyd@kernel.org>
Date: 2025-09-21 16:53:05
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Quoting Laura Nao (2025-09-15 08:19:21)
On MT8196, there are set/clr registers to control a shared PLL enable register. These are intended to prevent different masters from manipulating the PLLs independently. Add the corresponding en_set_reg and en_clr_reg fields to the mtk_pll_data structure. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Laura Nao <redacted> ---
Applied to clk-next