Re: [PATCH v6 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC
From: Stephen Boyd <sboyd@kernel.org>
Date: 2025-09-21 16:53:14
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Quoting Laura Nao (2025-09-15 08:19:22)
MT8196 uses a combination of set/clr registers to control the PLL enable state, along with a FENC bit to check the preparation status. Add new set of PLL clock operations with support for set/clr enable and FENC status logic. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Laura Nao <redacted> ---
Applied to clk-next