On 9/12/2025 5:57 PM, Konrad Dybcio wrote:

On 9/8/25 10:19 AM, Wasim Nazir wrote:

quoted

From: Sushrut Shree Trivedi <redacted>

Enable PCIe0 and PCIe1 along with the respective phy-nodes.

PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.

Signed-off-by: Sushrut Shree Trivedi <redacted>
Signed-off-by: Wasim Nazir <redacted>
---

[...]

quoted

+		perst-pins {
+			pins = "gpio2";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};

Pulling down an active-low pin is a bad idea

Ack, we should do pull up.
we took reference from the previous targets which seems to be wrong.
we will make it pull up.

Bjorn,
can you make this change while applying or shall we send new series.

- Sushrut

Konrad