On 9/8/25 10:19 AM, Wasim Nazir wrote:

From: Sushrut Shree Trivedi <redacted>

Enable PCIe0 and PCIe1 along with the respective phy-nodes.

PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.

Signed-off-by: Sushrut Shree Trivedi <redacted>
Signed-off-by: Wasim Nazir <redacted>
---

[...]

+		perst-pins {
+			pins = "gpio2";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};

Pulling down an active-low pin is a bad idea

Konrad