Hi Alexander,

On Wed, Aug 27, 2025 at 07:57:28AM +0200, Alexander Wilhelm wrote:

Hi Vladimir,

One of our hardware engineers has looked into the issue with the 100M link and
found the following: the Aquantia AQR115 always uses 2500BASE-X (GMII) on the
host side. For both 1G and 100M operation, it enables pause rate adaptation.
However, our MAC only applies rate adaptation for 1G links. For 100M, it uses a
10x symbol replication instead.

We’re exploring a workaround where the MAC is configured to believe it’s
operating at 1G, so it continues using pause rate adaptation, since flow control

Why at 1G and not at 2.5G?

is handled by the PHY. Given your deep expertise with Freescale MACs, I’d really
value your opinion on whether this approach makes sense or if you’ve seen
similar configurations before.

Best regards
Alexander Wilhelm

To be crystal clear, are you talking about the T1023 FMan mEMAC as being
the one which at 100M uses 10x symbol replication? Because the AQR115
PHY also contains a MAC block inside - this is what provides the MACsec
and rate adaptation functionality.

And if so, I don't know _how_ can that be - in mainline there is no code
that would reconfigure the SerDes lane from 2500base-x to SGMII. These
use different baud rates, so the lane would need to be moved to a
different PLL which provides the required clock net. Or are you using a
different kernel code base where this logic exists?

Also, I don't understand _why_ would the FMan mEMAC change its protocol
from 2500base-x to SGMII. It certainly doesn't do that by itself.
Rate adaptation is handled by phylink (phylink_link_up() sets rx_pause
unconditionally to true when in RATE_MATCH_PAUSE mode), and the MAC
should be kept in the same configuration for different media-side speeds.

Could you print phy_modes(state->interface) in memac_mac_config(), as
well as phy_modes(interface), speed, duplex, tx_pause, rx_pause in
memac_link_up()? This is to confirm that the mEMAC configuration is
identical when the PHY links at 1G and 100M.