Re: Aquantia PHY in OCSGMII mode?
From: Vladimir Oltean <olteanv@gmail.com>
Date: 2025-08-01 11:13:33
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On Thu, Jul 31, 2025 at 08:26:43PM +0100, Russell King (Oracle) wrote:
Essentially, in aqr107_fill_interface_modes() I do this: + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, MDIO_CTRL1_LPOWER); + mdelay(10); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x31a, 2);
By the way, you can add: #define VEND1_GLOBAL_STARTUP_RATE 0x031a #define VEND1_GLOBAL_STARTUP_RATE_1G 2 according to: https://github.com/nxp-qoriq/linux/blob/lf-6.12.20-2.0.0/drivers/net/phy/aquantia/aquantia.h#L45-L54
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10M, + VEND1_GLOBAL_CFG_SGMII_AN | + VEND1_GLOBAL_CFG_SERDES_MODE_SGMII); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_100M, + VEND1_GLOBAL_CFG_SGMII_AN | + VEND1_GLOBAL_CFG_SERDES_MODE_SGMII); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_1G, + VEND1_GLOBAL_CFG_SGMII_AN | + VEND1_GLOBAL_CFG_SERDES_MODE_SGMII); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, + VEND1_GLOBAL_CFG_SGMII_AN | + VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, + MDIO_CTRL1_LPOWER);