[PATCH v1 07/14] dt-bindings: display: mediatek,ufoe: Add mediatek,gce-client-reg property
From: Ariel D'Alessandro <hidden>
Date: 2025-08-20 17:16:42
Also in:
dri-devel, linux-arm-kernel, linux-clk, linux-devicetree, linux-gpio, linux-input, linux-media, linux-mediatek, linux-sound, lkml
Subsystem:
drm drivers, drm drivers and misc gpu patches, drm drivers for mediatek, open firmware and flattened device tree bindings, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Chun-Kuang Hu, Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Current, the DT bindings for Mediatek UFOe (Unified Frame Optimization engine) is missing the mediatek,gce-client-reg property. Add it and update the example as well. Signed-off-by: Ariel D'Alessandro <redacted> --- .../bindings/display/mediatek/mediatek,ufoe.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
index 61a5e22effbf2..ecb4c0359fec3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml@@ -64,6 +64,14 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/<chip>-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + required: - compatible - reg
@@ -77,7 +85,9 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/gce/mt8173-gce.h> #include <dt-bindings/power/mt8173-power.h> + soc { #address-cells = <2>; #size-cells = <2>;
@@ -88,5 +98,6 @@ examples: interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; };
--
2.50.1