On 7/14/25 3:50 PM, Andrew Lunn wrote:

On Mon, Jul 14, 2025 at 03:29:21PM -0700, Matthew Gerlach wrote:

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On 7/14/25 11:52 AM, Andrew Lunn wrote:

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On Mon, Jul 14, 2025 at 11:09:33AM -0700, Matthew Gerlach wrote:

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On 7/14/25 10:25 AM, Andrew Lunn wrote:
+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii";	/* Delays implemented by the IO ring of the Agilex5 SOCFPGA. */

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Please could you explain in more details what this means.
The normal meaning for 'rgmii' is that the PCB implements the

delay. I

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just want to fully understand what this IO ring is, and if it is part
of the PCB.
The IO ring is the logic in the Agilex5 that controls the pins on

the chip.

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It is this logic that sits between the MAC IP in the Agilex5 and the pins
connected to the PCB that is inserting the necessary delays. Technically the
PCB is not implementing the delays, but the "wires" between the MAC and the
external pins of the Agilex5 are implementing the delay. It seems to me that
"rgmii" is a more accurate description of the hardware than "rgmii-id" in
this case.

Is this delay hard coded, physically impossible to be disabled? A
syntheses option? Can it be changed at run time? Is the IO ring under
the control of a pinctrl driver? Can i use the standard 'skew-delay'
DT property to control this delay?

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The delay is not hard coded. It is a synthesis option that can be disabled.

Is there a register you can read which tells you if it is
enabled/disabled?

There are a collection of registers that could be examined to determine 
if delay has been inserted by IO ring.

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The delay in the IO ring can be disabled, but implementing the delay in the
IO ring allows for RGMII phys that don't implement the delay.

All RGMII PHYs which Linux support have the ability to do delays. And
we recommend the PHY does the delay, just to keep all systems the
same. There are a few exceptions, mostly because the MAC has hard
coded delays which cannot be disabled, but i guess 90% of systems have
the PHY doing the 2ns delays.

So, phy-mode should be set to 'rgmii-id', since the PCB does not add
the delays.

Understood. The PCB is not adding delays; so I'll change the phy-mode to 
be rgmii-id.

Ideally, you want to read from the IO ring if it is synthesised to do
the 2ns delays. Assuming it is enabled, you then mask the phy-mode
before connecting to the PHY, so avoiding double delays.

	Andrew

Currently, the registers in question are considered secure and only 
accessible by
Arm Trusted Firmware (ATF). I will investigate implementing this delay 
detecting
logic in a future patchset.

Thanks for the feedback,

Matthew Gerlach