On 7/14/25 11:52 AM, Andrew Lunn wrote:

On Mon, Jul 14, 2025 at 11:09:33AM -0700, Matthew Gerlach wrote:

quoted

On 7/14/25 10:25 AM, Andrew Lunn wrote:

quoted

quoted

+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii";	/* Delays implemented by the IO ring of the Agilex5 SOCFPGA. */

Please could you explain in more details what this means.

The normal meaning for 'rgmii' is that the PCB implements the delay. I
just want to fully understand what this IO ring is, and if it is part
of the PCB.

The IO ring is the logic in the Agilex5 that controls the pins on the chip.
It is this logic that sits between the MAC IP in the Agilex5 and the pins
connected to the PCB that is inserting the necessary delays. Technically the
PCB is not implementing the delays, but the "wires" between the MAC and the
external pins of the Agilex5 are implementing the delay. It seems to me that
"rgmii" is a more accurate description of the hardware than "rgmii-id" in
this case.

Is this delay hard coded, physically impossible to be disabled? A
syntheses option? Can it be changed at run time? Is the IO ring under
the control of a pinctrl driver? Can i use the standard 'skew-delay'
DT property to control this delay?

The delay is not hard coded. It is a synthesis option that can be 
disabled. The value cannot be changed at run time, and the IO ring is 
not under control of a pinctrl driver; so I don't think the standard 
'skew-delay' DT property can be used.

For silicon, if the delay cannot be removed, we have MAC drivers masks
the phy-mode to indicate it has implemented the delay. The MAC driver
should also return -EINVAL for any other RGMII mode than rgmii-id,
because that is the only RGMII mode which is possible.

The delay in the IO ring can be disabled, but implementing the delay in 
the IO ring allows for RGMII phys that don't implement the delay. 
Currently the driver, 
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c, and its bindings, 
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml, allow 
all rgmii phy-modes.

Since this is an FPGA, it is a bit more complex, so i want to fully
understand what is going on, what the different options are.

In this particular instantiation, the hard MAC controller is directly 
connected to pins via the IO ring, and the FPGA is not involved.

Matthew Gerlach

	Andrew