[PATCH 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
From: Matthew Gerlach <matthew.gerlach@altera.com>
Date: 2025-07-14 15:25:53
Also in:
linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/socfpga architecture, the rest · Maintainers:
Dinh Nguyen, Linus Torvalds
Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected to a RGMII PHY on a daughter card. The necessary clock delays are implemented between the MAC and PHY by the IO ring of the Agilex5. Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> --- .../boot/dts/intel/socfpga_agilex5_socdk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..5436646ec7ad 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts@@ -10,6 +10,9 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; }; chosen {
@@ -37,6 +40,21 @@ &gpio0 { status = "okay"; }; +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; /* Delays implemented by the IO ring of the Agilex5 SOCFPGA. */ + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &gpio1 { status = "okay"; };
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2.49.0