On Wed, Mar 05, 2025 at 02:43:52PM +0000, Russell King (Oracle) wrote:

On Wed, Mar 05, 2025 at 02:42:46PM +0530, Swathi K S wrote:

quoted

The FSD SoC contains two instance of the Synopsys DWC ethernet QOS IP core.
The binding that it uses is slightly different from existing ones because
of the integration (clocks, resets).

Signed-off-by: Swathi K S <redacted>

This looks much better!

Reviewed-by: Russell King (Oracle) <redacted>

Thanks!

Hi Swathi,

Please can you test with my TX clock gating series applied
( https://lore.kernel.org/r/Z9FVHEf3uUqtKzyt@shell.armlinux.org.uk (local) )
with STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP set as per the attached diff.
Please let me know whether this passes your testing, so I know whether
this platform supports it - please check that this results in a
message in the kernel log indicating "tx_clk_stop = 1". Thanks.

-- 
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