Re: [PATCH v8 05/27] cxl: move pci generic code
From: Alejandro Lucero Palau <hidden>
Date: 2025-01-08 14:39:52
Also in:
linux-cxl
On 1/8/25 05:19, Dan Williams wrote:
alejandro.lucero-palau@ wrote:quoted
From: Alejandro Lucero <redacted> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci.c implements the functionality for a Type3 device initialization. Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be exported and shared with CXL Type2 device initialization. Signed-off-by: Alejandro Lucero <redacted> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ben Cheatham <redacted> Reviewed-by: Fan Ni <redacted>This is the patch that causes the cxl-test build error...quoted
--- drivers/cxl/core/pci.c | 62 ++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 ++ drivers/cxl/pci.c | 71 ------------------------------------------ 3 files changed, 65 insertions(+), 71 deletions(-)diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bc098b2ce55d..3cca3ae438cd 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c@@ -1034,6 +1034,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); +/* + * Assume that any RCIEP that emits the CXL memory expander class code + * is an RCD + */ +bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, "CXL"); + +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map) +{ + struct cxl_port *port; + struct cxl_dport *dport; + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + port = cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);...and it is in part due to failing to notice that cxl_rcd_component_reg_phys() no longer needs to be exported once cxl_pci_setup_regs() move to the core. Please make sure there are not other occurrences of EXPORT_SYMBOL() cleanups that can be done in this series.
Sure.
Again, as I do not want to inflict cxl-test and --wrap= debugging on folks, here is an incremental fixup/cleanup below. Note how I fixed up the is_cxl_restricted() comment to make it relevant for the accelerator case. Please don't leave stale comments around when moving code.
OK.
Also note renaming the header guard to something more appropriate for include/cxl/pci.h. That should be folded back to patch1.
I'll fix it. Thanks!
quoted hunk ↗ jump to hunk
-- 8< --diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 800466f96a68..3b33470b8cbc 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h@@ -107,6 +107,8 @@ enum cxl_poison_trace_type { CXL_POISON_TRACE_CLEAR, }; +resource_size_t cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); long cxl_pci_get_latency(struct pci_dev *pdev); int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr,diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index aaea29bff0f1..afa3bd872dc0 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c@@ -1034,16 +1034,6 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} -EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, "CXL"); - static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, struct cxl_register_map *map, struct cxl_dport *dport)diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 6432a784f08b..0a218385c480 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c@@ -633,4 +633,3 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev, return CXL_RESOURCE_NONE; return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); } -EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL");diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 22e787748d79..8f241d87127a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h@@ -311,8 +311,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); int cxl_setup_regs(struct cxl_register_map *map, unsigned long *caps); struct cxl_dport; -resource_size_t cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport); int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1)diff --git a/include/cxl/pci.h b/include/cxl/pci.h index ad63560caa2c..efed17bc9274 100644 --- a/include/cxl/pci.h +++ b/include/cxl/pci.h@@ -1,8 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ -#ifndef __CXL_ACCEL_PCI_H -#define __CXL_ACCEL_PCI_H +#ifndef __LINUX_CXL_PCI_H__ +#define __LINUX_CXL_PCI_H__ + +#include <linux/pci.h> + +/* + * Assume that the caller has already validated that @pdev has CXL + * capabilities, any RCIEp with CXL capabilities is treated as a + * Restricted CXL Device (RCD) and finds upstream port and endpoint + * registers in a Root Complex Register Block (RCRB) + */ +static inline bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index b1256fee3567..e20d0e767574 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild@@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready ldflags-y += --wrap=cxl_hdm_decode_init ldflags-y += --wrap=cxl_dvsec_rr_decode ldflags-y += --wrap=devm_cxl_add_rch_dport -ldflags-y += --wrap=cxl_rcd_component_reg_phys ldflags-y += --wrap=cxl_endpoint_parse_cdat ldflags-y += --wrap=cxl_dport_init_ras_reportingdiff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 450c7566c33f..af7a5ae09ef8 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c@@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport) -{ - int index; - resource_size_t component_reg_phys; - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - - if (ops && ops->is_mock_port(dev)) - component_reg_phys = CXL_RESOURCE_NONE; - else - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); - put_cxl_mock_ops(index); - - return component_reg_phys; -} -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); - void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) { int index;