[PATCH v2 7/7] riscv: dts: microchip: add missing CAN bus clocks
From: Conor Dooley <conor@kernel.org>
Date: 2024-01-22 12:20:45
Also in:
linux-can, linux-clk, linux-devicetree, linux-riscv, lkml
Subsystem:
risc-v architecture, risc-v microchip support, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Daire McNamara, Linus Torvalds
From: Conor Dooley <conor.dooley@microchip.com>
The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a
CAN bus clock. The bus clock was omitted when the binding was written,
but is required for operation. Make up for lost time and add to the DT.
Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 266489d43912..4d70df0f908c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi@@ -416,7 +416,7 @@ i2c1: i2c@2010b000 { can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled";
@@ -425,7 +425,7 @@ can0: can@2010c000 { can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled";
--
2.43.0