On Tue, Aug 22, 2023 at 11:30 AM Alexander Duyck
[off-list ref] wrote:

On Tue, Aug 22, 2023 at 8:38 AM Jakub Kicinski [off-list ref] wrote:

quoted

On Tue, 22 Aug 2023 17:21:35 +0800 Yunsheng Lin wrote:

quoted

quoted

.. we should also add a:

    WARN_ONCE(1, "misaligned DMA address, please report to netdev@");

As the CONFIG_PHYS_ADDR_T_64BIT seems to used widely in x86/arm/mips/powerpc,
I am not sure if we can really make the above assumption.

https://elixir.free-electrons.com/linux/v6.4-rc6/K/ident/CONFIG_PHYS_ADDR_T_64BIT

Huh, it's actually used a lot less than I anticipated!

None of the x86/arm/mips/powerpc systems matter IMHO - the only _real_
risk is something we don't know about returning non-aligned addresses.

Unless we know about specific problems I'd suggest we took the simpler
path rather than complicating the design for systems which may not
exist.

Alex, do you know of any such cases? Some crazy swiotlb setting?
WDYT about this in general?

There may be scenarios where if bounce buffers are used the page may
not be aligned. It all comes down to how
swiotlb_tbl_map_single(https://elixir.free-electrons.com/linux/v6.5-rc7/C/ident/swiotlb_tbl_map_single)
is called. In the IOMMU case it looks like they take the extra step of
passing an alignment value, but it looks like for the other two cases
they don't.

Changing that behavior wouldn't take much though. Basically we would
just need to do something like look at the size and address and if
they are both page aligned then we could specify a page alignment for
the DMA mapping.

Actually I take that back. It looks like in the bounce case there is
already code that will look for PAGE_SIZE aligned blocks if the
request is for PAGE_SIZE or larger. So there shouldn't be any cases
where a PAGE_SIZE request is not PAGE_SIZE aligned in DMA that I am
aware of.