RE: [PATCH 5/5] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch

Hi Andrew,

Thank you for your review!

From: Andrew Lunn, Sent: Tuesday, September 13, 2022 9:16 AM

quoted

+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			phy-handle = <&etha0>;
+			phy-mode = "sgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			etha0: ethernet-phy@0 {
+				reg = <1>;

reg = 1 means you should have @1.

I'll fix it.

quoted

+				compatible = "ethernet-phy-ieee802.3-c45";
+			};
+		};

You are mixing Ethernet and MDIO properties in one node. Past
experience says this is a bad idea, particularly when you have
switches involved. I would suggest you add an mdio container:

quoted

+		port@1 {
+			reg = <1>;
+			phy-handle = <&etha1>;
+			phy-mode = "sgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;

                        mdio {

quoted

+			    etha1: ethernet-phy@1 {
+				reg = <2>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+			    };

                        };

quoted

+		};

Thank you for the suggestion. I'll fix it.

quoted

+		port@2 {
+			reg = <2>;
+			phy-handle = <&etha2>;
+			phy-mode = "sgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			etha2: ethernet-phy@2 {
+				reg = <3>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+			};
+		};

I find it interesting you have PHYs are address 1, 2, 3, even though
they are on individual busses. Why pay for the extra pullup/down
resistors when they could all have the same address?

I don't know why. But, the board really configured such PHY addresses...

Best regards,
Yoshihiro Shimoda

	  Andrew