Re: [PATCH net-next v3 13/14] ravb: Update ravb_emac_init_gbeth()
From: Sergey Shtylyov <hidden>
Date: 2021-10-12 17:34:16
Also in:
linux-renesas-soc
On 10/12/21 7:36 PM, Biju Das wrote:
This patch enables Receive/Transmit port of TOE and removes the setting of promiscuous bit from EMAC configuration mode register. This patch also update EMAC configuration mode comment from "PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through".
I'm not sure why you set ECMR.RCPT while you don't have the checksum offloaded...
quoted hunk ↗ jump to hunk
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v2->v3: * Enabled TPE/RPE of TOE, as disabling causes loopback test to fail * Documented CSR0 register bits * Removed PRM setting from EMAC configuration mode * Updated EMAC configuration mode. v1->v2: * No change V1: * New patch. --- drivers/net/ethernet/renesas/ravb.h | 6 ++++++ drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-)diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 69a771526776..08062d73df10 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h@@ -204,6 +204,7 @@ enum ravb_reg { TLFRCR = 0x0758, RFCR = 0x0760, MAFCR = 0x0778, + CSR0 = 0x0800, /* RZ/G2L only */ };@@ -964,6 +965,11 @@ enum CXR31_BIT { CXR31_SEL_LINK1 = 0x00000008, }; +enum CSR0_BIT { + CSR0_TPE = 0x00000010, + CSR0_RPE = 0x00000020, +}; +
Is this really needed if you have ECMR.RCPT cleared? [...] MBR, Sergey