Re: stmmac: Disappointing or normal DMA performance?

Yes, I have played with the RX coal values. My understanding is that
there is a hardware watchdog to trigger the DMA IRQ with a maximum
value of MAX_DMA_RIWT == 0xff.

rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);

if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
return -EINVAL;

This seems to lead to 326us. My 30000 frames per second arrive every
33us and 326 / 33 ~ 10 frames per interrupt...

In other words, I have the feeling that the answer to my subject
question is both: it's normal and it's disappointing.

Can ST confirm the hardware limit (the internal RX FIFO I guess) that
it's not possible to do better than 10 1280-byte frames per DMA
interrupt in my case?

John

On Wed, Sep 22, 2021 at 7:12 AM Andrew Lunn [off-list ref] wrote:

quoted

Is there a way to increase the ratio of packets / IRQs? I want fewer
IRQs with more packets as the current performance overloads my
embedded chip,

Have you played with ethtool -c/-C.

     Andrew