stmmac: Disappointing or normal DMA performance?

3 messages, 2 authors, 2021-09-22 · open the first message on its own page

stmmac: Disappointing or normal DMA performance?

From: John Smith <hidden>
Date: 2021-09-22 08:49:09

I have a one-way 300Mbs traffic RGMII arriving at a stmmac version
3.7, in the form of 30000 1280-byte frames per second, evenly spread.

In NAPI poll mode, at each DMA interrupt, I get around 10 frames. More
precisely:

In stmmac_rx of stmmac_main.c:

static int stmmac_rx(struct stmmac_priv *priv, int limit) {
...
while (count < limit)

count is around 10 when NAPI limit/weight is 64. It means that I get
3000 DMA IRQs per second for my 30000 packets.

I have tried different settings but I can't do anything better.
"Better" meaning that I would like to have fewer interrupts per
second, so a higher number of frames on each interrupt in order to
minimize the load transferred to my CPU.

Everything else being the same, if I send 10000 1280x3=3840-byte
frames per second, I get around 3 or 4 frames per interrupt.

Is there a way to increase the ratio of packets / IRQs? I want fewer
IRQs with more packets as the current performance overloads my
embedded chip,

John

Re: stmmac: Disappointing or normal DMA performance?

From: Andrew Lunn <andrew@lunn.ch>
Date: 2021-09-22 14:12:07

Is there a way to increase the ratio of packets / IRQs? I want fewer
IRQs with more packets as the current performance overloads my
embedded chip,
Have you played with ethtool -c/-C.

     Andrew

Re: stmmac: Disappointing or normal DMA performance?

From: John Smith <hidden>
Date: 2021-09-22 18:59:34

Yes, I have played with the RX coal values. My understanding is that
there is a hardware watchdog to trigger the DMA IRQ with a maximum
value of MAX_DMA_RIWT == 0xff.

rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);

if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
return -EINVAL;

This seems to lead to 326us. My 30000 frames per second arrive every
33us and 326 / 33 ~ 10 frames per interrupt...

In other words, I have the feeling that the answer to my subject
question is both: it's normal and it's disappointing.

Can ST confirm the hardware limit (the internal RX FIFO I guess) that
it's not possible to do better than 10 1280-byte frames per DMA
interrupt in my case?

John

On Wed, Sep 22, 2021 at 7:12 AM Andrew Lunn [off-list ref] wrote:
quoted
Is there a way to increase the ratio of packets / IRQs? I want fewer
IRQs with more packets as the current performance overloads my
embedded chip,
Have you played with ethtool -c/-C.

     Andrew
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