Re: [PATCH v2 3/5] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2021-07-20 10:42:26
Also in:
linux-can, linux-clk, linux-devicetree, linux-renesas-soc, lkml
On Mon, Jul 19, 2021 at 4:39 PM Lad Prabhakar [off-list ref] wrote:
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is sourced from P0_DIV2 referenced from HW manual Rev.0.50. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-r9a07g044-dt-binding-defs, to be shared by
renesas-clk-for-v5.15 and renesas-devel for v5.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds