[PATCH v2 4/5] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2
flat view
STALE1910d
LANDED: 4 (4M)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: 2021-07-19 14:40:07
Also in:
linux-can, linux-clk, linux-devicetree, linux-renesas-soc, lkml
Subsystem:
common clk framework, renesas clock drivers, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Geert Uytterhoeven, Linus Torvalds
Revision v2 of 2 in this series; 1 review trailer; landed in mainline as d28b1e03dc8d on 2021-07-26.
Revisions (2)
- v1 [diff vs current]
- v2 current
Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK to R9A07G044_CLK_P0_DIV2. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f4ebbde358c6..523521a87713 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c@@ -16,7 +16,7 @@ enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A07G044_OSCCLK, + LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2, /* External Input Clocks */ CLK_EXTAL,
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
--
2.17.1