Re: [PATCH net-next 03/13] net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually MDIO_MMD_VEND2
From: Florian Fainelli <f.fainelli@gmail.com>
Date: 2021-05-25 02:19:29
On 5/24/2021 4:22 PM, Vladimir Oltean wrote:
From: Vladimir Oltean <vladimir.oltean@nxp.com> Looking at the SGMII PCS from SJA1110, which is accessed indirectly through a different base address as can be seen in the next patch, it appears odd that the address accessed through indirection still references the base address from the SJA1105S register map (first MDIO register is at 0x1f0000), when it could index the SGMII registers starting from zero. Except that the 0x1f0000 is not a base address at all, it seems. It is 0x1f << 16 | 0x0000, and 0x1f is coding for the vendor-specific MMD2. So, it turns out, the Synopsys PCS implements all its registers inside the vendor-specific MMDs 1 and 2 (0x1e and 0x1f). This explains why the PCS has no overlaps (for the other MMDs) with other register regions of the switch (because no other MMDs are implemented). Change the code to remove the SGMII "base address" and explicitly encode the MMD for reads/writes. This will become necessary for SJA1110 support. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> ---
[snip]
quoted hunk ↗ jump to hunk
@@ -1905,7 +1904,9 @@ int sja1105_static_config_reload(struct sja1105_private *priv, mac[i].speed = SJA1105_SPEED_AUTO; if (sja1105_supports_sgmii(priv, i)) - bmcr[i] = sja1105_sgmii_read(priv, i, MII_BMCR); + bmcr[i] = sja1105_sgmii_read(priv, i, + MDIO_MMD_VEND2, + MDIO_CTRL1);
This appears different from what you had before? -- Florian