On Mon, Jan 25, 2021 at 11:59 AM Jason Gunthorpe [off-list ref] wrote:

Every writable data mandated by the PCI spec requires very expensive
on-die SRAM to store it.

That's an implementation decision. Nothing mandates that the state has
to physically exist in the same structure, only that reads and writes
are appropriately responded to. Parts that are read only could be
generated on the fly and writes can be stored more efficiently.

We've seen Intel drivers that show their SIOV ADIs don't even have a
register file and the only PCI presence is just a write-only doorbell
page in the BAR.

Right, but presumably it still needs to be at least a page. And,
nothing says your device's VF BAR protocol can't be equally simple.

It is hard to argue a write-only register in a BAR page vs all the
SRIOV trappings when it comes to HW cost.

Say it's double the cost? I don't know that it is, but does that
warrant the additional complexity of SFs? We should try to quantify.

Regards,
Edwin Peer