On Mon, Dec 18, 2017 at 07:21:30PM +0800, Greentime Hu wrote:

Hi, Guo Ren:

2017-12-18 17:08 GMT+08:00 Guo Ren [off-list ref]:

quoted

Hi Greentime,

On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
[...]

quoted

diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c

[...]

quoted

+void *kmap(struct page *page)
+{
+     unsigned long vaddr;
+     might_sleep();
+     if (!PageHighMem(page))
+             return page_address(page);
+     vaddr = (unsigned long)kmap_high(page);

Here should invalid the cpu_mmu_tlb's entry, Or invalid it in the
set_pte().

eg:
vaddr0 = kmap(page0)
*vaddr0 = val0 //It will cause tlb-miss, and hard-refill to MMU-tlb
kunmap(page0)
vaddr1 = kmap(page1) // Mostly vaddr1 = vaddr0
val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
                last expired vaddr0's entry is left in CPU-MMU-tlb.

Thanks.
I will add __nds32__tlbop_inv(vaddr); to invalidate this mapping
before retrun vaddr.

Sorry, perhaps I'm wrong. See
kmap->kmap_high->map_new_virtual->get_next_pkmap_nr(color).

Seems pkmap will return the vaddr by vaddr + 1 until
no_more_pkmaps(), and then flush_all_zero_pkmaps.
Just kmap_atomic need it, and you've done.

But I don't know why mips need flush_tlb_one in
arch/mips/mm/highmem.c:kmap(). VIPT? but kmap give the get_pkmap_color
for aliasing.

Best Regards
 Guo Ren