This is an attempt to resurrect the mainline WNR854T support (I had no
luck getting a non-DT kernel to boot). First 2 patches are trivial,
the next 3 add DT bindings for the SoC, then the old board file is
swapped out for DT. The final 3 patches configure the PHY leds as
Netgear intended.
There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.
I've not tried to move the PCI support into DT yet. Are there other
branches that tackle this already?
Patch 8 is the least-intrusive patch I could think of to find the PHY
node, but I'm not sure it's the best approach. I tried to get
dsa_slave_phy_connect() to wire up the OF node correctly[1], but doing
this properly would require changes to the mdiobus api, any exposed
methods register all nodes in an MDIO bus node, which doesn't exist in
this case.
Applied against v4.6 mainline, .config:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/kernel-config.txt
Log output:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/u-boot.dmesg.txt
The patchset is also available here:
https://github.com/lentinj/linux/commits/wnr854t-support-v0a
To use the supplied PCI Wifi card see the following patch:
https://github.com/lentinj/linux/commit/d6b7b4695b7dcbf36d0663aea9cb4ecd65a1ada8
...but this is probably a matter for another thread.
Cheers,
[0] http://thread.gmane.org/gmane.linux.network/120616/focus=121320
[1] https://github.com/lentinj/linux/commit/a4bceebb08ecdc25a4d49e23f2abad214868460e
Jamie Lentin (10):
arm: orion5x: Add required properties for orion-wdt to DT node
arm: orion5x: Add documentation for SoC and board bindings
arm: orion5x: Add clk support for mv88f5181
arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
arm: orion5x: Add DT include for mv88f5181
arm: orion5x: Add DT-based support for Netgear WNR854T
arm: orion5x: Remove old non-DT-based WNR854T support
net: phy: Try looking for a phy-handle property to find the OF node
net: phy: Re-attempt custom DT configuration after configuration
arm: orion5x: Configure Netgear WNR854T network port LEDs
.../bindings/arm/marvell/marvell,orion5x.txt | 25 +++
.../devicetree/bindings/clock/mvebu-core-clock.txt | 1 +
.../bindings/pinctrl/marvell,orion-pinctrl.txt | 4 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 35 +++
arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 245 +++++++++++++++++++++
arch/arm/boot/dts/orion5x.dtsi | 3 +-
arch/arm/mach-orion5x/Kconfig | 6 +
arch/arm/mach-orion5x/Makefile | 2 +-
arch/arm/mach-orion5x/board-wnr854t.c | 78 +++++++
arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------
drivers/clk/mvebu/orion.c | 70 ++++++
drivers/net/phy/marvell.c | 26 ++-
drivers/pinctrl/mvebu/pinctrl-orion.c | 23 +-
14 files changed, 498 insertions(+), 206 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c
--
2.8.1
@@ -0,0 +1,78 @@+/*+*NetgearWNR854TPCIsetup+*+*ThisfileislicensedunderthetermsoftheGNUGeneralPublic+*Licenseversion2.Thisprogramislicensed"as is"withoutany+*warrantyofanykind,whetherexpressorimplied.+*/+#include<linux/gpio.h>+#include<linux/platform_device.h>+#include<linux/pci.h>+#include<asm/mach/pci.h>+#include"common.h"+#include"orion5x.h"++#define WNR854T_PCI_SLOT0_OFFS 7+#define WNR854T_PCI_SLOT0_IRQ_PIN 4++staticvoid__initwnr854t_pci_preinit(void)+{+intpin;++/*+*ConfigurePCIGPIOIRQpins+*/+pin=WNR854T_PCI_SLOT0_IRQ_PIN;+if(gpio_request(pin,"PCI Int")==0){+if(gpio_direction_input(pin)==0){+irq_set_irq_type(gpio_to_irq(pin),IRQ_TYPE_LEVEL_LOW);+}else{+pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",+pin);+gpio_free(pin);+}+}else{+pr_err("wnr854t_pci_preinit failed to request gpio %d\n",pin);+}+}++staticint__initwnr854t_pci_map_irq(conststructpci_dev*dev,u8slot,+u8pin)+{+intirq;++/*+*Checkfordeviceswithhard-wiredIRQs.+*/+irq=orion5x_pci_map_irq(dev,slot,pin);+if(irq!=-1)+returnirq;++/*+*PCIIRQsareconnectedviaGPIOs+*/+switch(slot-WNR854T_PCI_SLOT0_OFFS){+case0:+returngpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);+default:+return-1;+}+}++staticstructhw_pciwnr854t_pci__initdata={+.nr_controllers=2,+.preinit=wnr854t_pci_preinit,+.setup=orion5x_pci_sys_setup,+.scan=orion5x_pci_sys_scan_bus,+.map_irq=wnr854t_pci_map_irq,+};++staticint__initwnr854t_pci_init(void)+{+if(of_machine_is_compatible("netgear,wnr854t"))+pci_common_init(&wnr854t_pci);++return0;+}+/* NB: Use late_initcall so we can gpio_request() without being deferred */+late_initcall(wnr854t_pci_init);
orion-wdt refuses to start without these properties defined, so lift
definitions out of kirkwood/dove.dtsi
Signed-off-by: Jamie Lentin <redacted>
---
arch/arm/boot/dts/orion5x.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Referring to values in the u-boot port, add support for the mv88f5181
Signed-off-by: Jamie Lentin <redacted>
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 1 +
drivers/clk/mvebu/orion.c | 70 ++++++++++++++++++++++
2 files changed, 71 insertions(+)
If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
not exist in devicetree, but there may be a reference to the PHY node
on the physical MDIO bus to use.
Signed-off-by: Jamie Lentin <redacted>
---
drivers/net/phy/marvell.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)*/staticintmarvell_of_reg_init(structphy_device*phydev){-const__be32*paddr;+const__be32*paddr=NULL;intlen,i,saved_page,current_page,page_changed,ret;+structdevice_node*phy_dn;++if(phydev->mdio.dev.of_node)+paddr=of_get_property(phydev->mdio.dev.of_node,+"marvell,reg-init",&len);+elseif(phydev->attached_dev->dev.of_node){+/* A DSA slave-mii-bus has no OF node, but the PHY might */+phy_dn=of_parse_phandle(phydev->attached_dev->dev.of_node,+"phy-handle",0);+if(phy_dn){+paddr=of_get_property(phy_dn,+"marvell,reg-init",&len);+of_node_put(phy_dn);+}+}-if(!phydev->mdio.dev.of_node)-return0;--paddr=of_get_property(phydev->mdio.dev.of_node,-"marvell,reg-init",&len);if(!paddr||len<(4*sizeof(*paddr)))return0;
marvell,reg-init is generally used to apply a custom LED configuration
on boot. However this is then blatted in m88e1121_config_aneg when the
interface is brought up. Re-apply any custom configuration afterwards,
to keep custom LED configuration.
Signed-off-by: Jamie Lentin <redacted>
---
drivers/net/phy/marvell.c | 4 ++++
1 file changed, 4 insertions(+)
@@ -0,0 +1,23 @@+Marvell Orion SoC Family Device Tree Bindings+---------------------------------------------++Boards with a SoC of the Marvell Orion family, eg 88f5181++* Required root node properties:+compatible: must contain "marvell,orion5x"++In addition, the above compatible shall be extended with the specific+SoC. Currently known SoC compatibles are:++"marvell,orion5x-88f5182"++And in addition, the compatible shall be extended with the specific+board. Currently known boards are:++"buffalo,lsgl"+"buffalo,lswsgl"+"buffalo,lswtgl"+"lacie,ethernet-disk-mini-v2"+"lacie,d2-network"+"marvell,rd-88f5182-nas"+"maxtor,shared-storage-2"
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x" In addition, the above compatible shall be extended with the specific SoC. Currently known SoC compatibles are:+"marvell,orion5x-88f5181" "marvell,orion5x-88f5182" And in addition, the compatible shall be extended with the specific
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.
Signed-off-by: Jamie Lentin <redacted>
---
.../bindings/pinctrl/marvell,orion-pinctrl.txt | 4 ++--
drivers/pinctrl/mvebu/pinctrl-orion.c | 23 +++++++++++-----------
2 files changed, 14 insertions(+), 13 deletions(-)
@@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties:-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",- "marvell,88f5281-pinctrl"+- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",+ "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl" - reg: two register areas, the first one describing the first two contiguous MPP registers, and the second one describing the single
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:05:33
On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
Copy the format for kirkwood/dove to orion5x
Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
Reviewed-by: Andrew Lunn <redacted>
Andrew
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From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:10:22
On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
Referring to values in the u-boot port, add support for the mv88f5181
Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
Reviewed-by: Andrew Lunn <redacted>
Andrew
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From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:15:39
On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.
Good, you add a new compatibile string. So it if turns out they are
not identical, we can fix it later without causing problems.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x" In addition, the above compatible shall be extended with the specific SoC. Currently known SoC compatibles are:+"marvell,orion5x-88f5181" "marvell,orion5x-88f5182" And in addition, the compatible shall be extended with the specific
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Documentation/devicetree/bindings/mtd/partition.txt says the
partitions should be placed under a partitions node. There are some
conditions when that does not work. So please try it, and if it does
not, ignore my comment...
Nice to see the comment.
Andrew
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From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:37:10
On Sat, Jul 16, 2016 at 03:29:05PM +0100, Jamie Lentin wrote:
Again, you need a commit log. It could be something like:
The setup file for the wnr854t has bit rotted to such an extent it no
longer works. Replace it with a working device tree description.
Andrew
Ah! I think i interpreted that wrong. This does not reset the Ethernet
switch. It is actually a switch on the front to reset the whole box?
How about calling it button, not switch?
Andrew
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:44:24
On Sat, Jul 16, 2016 at 03:29:06PM +0100, Jamie Lentin wrote:
If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
not exist in devicetree, but there may be a reference to the PHY node
on the physical MDIO bus to use.
O.K, i see what you are trying to achieve, it makes sense, but sorry,
NACK.
There is however a nice solution :-)
If you look in net-next, you will notice a big change to DSA. There is
a new binding, and the mv88e6xxx driver now exports the switch
internal MDIO bus just like any other MDIO bus. So you can have a phy
on the MDIO bus, and that phy can have "marvell,reg-init" properties.
Andrew
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)*/staticintmarvell_of_reg_init(structphy_device*phydev){-const__be32*paddr;+const__be32*paddr=NULL;intlen,i,saved_page,current_page,page_changed,ret;+structdevice_node*phy_dn;++if(phydev->mdio.dev.of_node)+paddr=of_get_property(phydev->mdio.dev.of_node,+"marvell,reg-init",&len);+elseif(phydev->attached_dev->dev.of_node){+/* A DSA slave-mii-bus has no OF node, but the PHY might */+phy_dn=of_parse_phandle(phydev->attached_dev->dev.of_node,+"phy-handle",0);+if(phy_dn){+paddr=of_get_property(phy_dn,+"marvell,reg-init",&len);+of_node_put(phy_dn);+}+}-if(!phydev->mdio.dev.of_node)-return0;--paddr=of_get_property(phydev->mdio.dev.of_node,-"marvell,reg-init",&len);if(!paddr||len<(4*sizeof(*paddr)))return0;
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-16 16:45:06
On Sat, Jul 16, 2016 at 03:29:07PM +0100, Jamie Lentin wrote:
marvell,reg-init is generally used to apply a custom LED configuration
on boot. However this is then blatted in m88e1121_config_aneg when the
interface is brought up. Re-apply any custom configuration afterwards,
to keep custom LED configuration.
This has been fixed in net-next.
Andrew
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This one too...
[...]
MBR, Sergei
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The other patches all appear good to me, but I find this one suspicious.
Why are you not using the device tree for probing PCI? Is there anything
missing in drivers/pci/host/pci-mvebu.c, or do you just need help
describing it in DT?
Arnd
There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.
Hi Jamie
So it is 6131? So part of the 6185 family.
I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.
Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx.
The reg, stats, and atu would be interesting.
Andrew
The other patches all appear good to me, but I find this one suspicious.
Why are you not using the device tree for probing PCI? Is there anything
missing in drivers/pci/host/pci-mvebu.c, or do you just need help
describing it in DT?
Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port
as well as a PCIe port. Given no other orion5x boards seem to use
pci-mvebu, I'm assuming there's work to be done before the PCI port can be
used via. pci-mvebu.c
This is something I can look into if there aren't patches out there, but
wanted to get the rest into a reasonable state first.
There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.
Hi Jamie
So it is 6131? So part of the 6185 family.
Yes, that's what's detected and the OpenWRT page says 88E6131-LAR1. And my
test setup looks like:
88e6131
|- lan1:10.100.1.55 <-- switch --> eth0:10.100.1.41 -|
|- lan4:10.100.4.55 <-- cable --> enp0:10.100.4.41 -|
laptop
enp0 is a 100M USB network card, the switch is gigabit and on the rest of
my network here, so there's assorted background broadcast chatter. If the
noise is confusing matters then can disconnect it.
Firstly I've tried to to rebase against net-next[0], but after adding 6131
to mv88e6xxx_of_match, &chip->ppu_work seems to be causing a NULL pointer
ooops. I'll assume it's not done yet and ignore net-next for now.
I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.
Okay, back to my original wnr854t-support-v0a branch based on 4.6,
switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
add support, but there's no traffic in/out of any port. tcpdump on the
underlying ethernet port shows encapsulated broadcast traffic, e.g. this
ARP request from enp0:10.100.4.41:
00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast, ethertype
Unknown (0xc008), length 64:
0x0000: 0000 0806 0001 0800 0604 0001 1aff 0ffe ................
0x0010: 1022 0a64 0429 0000 0000 0000 0a64 0437 .".d.).......d.7
0x0020: 0000 0000 0000 0000 0000 0000 0000 0000 ................
0x0030: 0000 ..
...but no unicast traffic.
Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx.
The reg, stats, and atu would be interesting.
Firstly I've tried to to rebase against net-next[0], but after
adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
causing a NULL pointer ooops. I'll assume it's not done yet and
ignore net-next for now.
You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
with the mv88e6085. Just use the compatible string of
"marvell,mv88e6085". So far, ever Marvell chip we support is
compatible with the mv88e6085, in terms of probing. Once the driver
has probed, and read the device ID from a register, it knows enough to
decide for itself what features the chip has.
In order to get the LEDs working as you want, you are going to have to
use the new binding. So i would suggest sticking with that.
quoted
I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.
Okay, back to my original wnr854t-support-v0a branch based on 4.6,
switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
add support, but there's no traffic in/out of any port. tcpdump on
the underlying ethernet port shows encapsulated broadcast traffic,
e.g. this ARP request from enp0:10.100.4.41:
00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
ethertype Unknown (0xc008), length 64:
0x0000: 0000 0806 0001 0800 0604 0001 1aff 0ffe ................
0x0010: 1022 0a64 0429 0000 0000 0000 0a64 0437 .".d.).......d.7
0x0020: 0000 0000 0000 0000 0000 0000 0000 0000 ................
0x0030: 0000 ..
...but no unicast traffic.
Uh, that does not look like EDSA tagging. Expect an ethertype of
0xdada. Also, if you get the latest tcpdump sources, it knows how to
decode the additional EDSA header which is added.
quoted
Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx.
The reg, stats, and atu would be interesting.
Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
LEDs, cherry-picked the above commit. Pushed the result if it's
useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
net-next.
Yes, the debug code is a real pain. Something i'm working on in the
background, get something generic which is acceptable for mainline.
+ port@3 {
+ reg = <3>;
+ label = "cpu";
+ ethernet = <ð>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
You don't need a fixed-link here. The cpu port is automatically
configured fixed at the highest speed the port will do.
However,
ð {
status = "okay";
- ethernet-port@0 {
- speed = <1000>;
- duplex = <1>;
- };
};
here you do need the fixed link, otherwise it thinks there is a PHY
connected and tried to do auto-negotiation. That will never work.
Andrew
From: Rob Herring <robh@kernel.org> Date: 2016-07-17 20:36:01
On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
Copy the format for kirkwood/dove to orion5x
Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
.../bindings/arm/marvell/marvell,orion5x.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
Acked-by: Rob Herring <redacted>
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From: Rob Herring <robh@kernel.org> Date: 2016-07-17 20:36:48
On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
Referring to values in the u-boot port, add support for the mv88f5181
Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 1 +
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From: Rob Herring <robh@kernel.org> Date: 2016-07-17 20:40:19
On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
quoted hunk
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.
Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
.../bindings/pinctrl/marvell,orion-pinctrl.txt | 4 ++--
drivers/pinctrl/mvebu/pinctrl-orion.c | 23 +++++++++++-----------
2 files changed, 14 insertions(+), 13 deletions(-)
@@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties:-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",- "marvell,88f5281-pinctrl"+- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",+ "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"
Please reformat to one per line. Otherwise,
Acked-by: Rob Herring <redacted>
- reg: two register areas, the first one describing the first two
contiguous MPP registers, and the second one describing the single
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On Sunday, July 17, 2016 10:39:01 AM CEST Jamie Lentin wrote:
On Sat, 16 Jul 2016, Arnd Bergmann wrote:
quoted
The other patches all appear good to me, but I find this one suspicious.
Why are you not using the device tree for probing PCI? Is there anything
missing in drivers/pci/host/pci-mvebu.c, or do you just need help
describing it in DT?
Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port
as well as a PCIe port. Given no other orion5x boards seem to use
pci-mvebu, I'm assuming there's work to be done before the PCI port can be
used via. pci-mvebu.c
This is something I can look into if there aren't patches out there, but
wanted to get the rest into a reasonable state first.
Ok, I see your point. However, we also don't have any other Orion5x machines
using DT that rely on old probe method, and I this is something that
is particularly hard to retrofit later.
I would assume that the PCIe port should work out of the box with the driver
we have, but the PCI controller does not, and it will require some work.
Looking at https://wiki.openwrt.org/toh/netgear/wnr854t, I assume that
you want only PCI but not PCIe, correct?
The good news is that we can completely separate the two, we just have two
different PCI domains if both are enabled, so we just need to add a new
driver for the PCI port to drivers/pci/host. The pci_ops can be copied
from the existing driver, although a couple of minor cleanups would be
possible. The special handling of bus numbers and the rc_pci_fixup()
can probably just go away, and the latter part is particularly
important, because building a kernel with the fixup included might
break any system with a Marvell host bridge.
We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).
Arnd
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+ model = "Netgear WNR854-t";
+ compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+ "marvell,orion5x";
+
+ memory {
+ reg = <0x00000000 0x2000000>; /* 32 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ linux,stdout-path = &uart0;
There should only be at most 1 kconfig entry for all orion5x DT based
platforms.
+ bool "Netgear WNR854T (Flattened Device Tree)"
+ help
+ Say 'Y' here if you want your kernel to support the
+ Netgear WNR854T platform.
+
config MACH_WNR854T
bool "Netgear WNR854T"
help
I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.
Definitely not impossible to implement, but the driver doesn't work
as-is.
We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).
MBus windows are needed. See:
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
ORION5X_PCI_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
ORION_MBUS_PCI_MEM_ATTR,
ORION5X_PCI_MEM_PHYS_BASE,
ORION5X_PCI_MEM_SIZE);
in orion5x_setup_wins().
Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
quoted
I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.
Definitely not impossible to implement, but the driver doesn't work
as-is.
Ok.
quoted
We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).
MBus windows are needed. See:
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
ORION5X_PCI_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
ORION_MBUS_PCI_MEM_ATTR,
ORION5X_PCI_MEM_PHYS_BASE,
ORION5X_PCI_MEM_SIZE);
in orion5x_setup_wins().
Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.
Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.
Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.
I was also hoping that we could get to the point where pci_common_init()
is only used for legacy machines without DT and without multiplatform,
it seems I missed a couple of users here.
Arnd
Firstly I've tried to to rebase against net-next[0], but after
adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
causing a NULL pointer ooops. I'll assume it's not done yet and
ignore net-next for now.
You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
with the mv88e6085. Just use the compatible string of
"marvell,mv88e6085". So far, ever Marvell chip we support is
compatible with the mv88e6085, in terms of probing. Once the driver
has probed, and read the device ID from a register, it knows enough to
decide for itself what features the chip has.
Okay, besides the DT mistakes you mention below (changes are pushed to the
same branch), I've worked out out what my problem was here. The switch was
probed before the ethernet device is available, so mv88e6xxx_probe() has
to back out with EPROBE_DEFER at mv88e6xxx_register_switch().
However mv88e6xxx_mdio_unregister() doesn't tidy up fully. The following
lets me boot, but I'm not really clear what the usleep is helping solve
and don't like it:
In order to get the LEDs working as you want, you are going to have to
use the new binding. So i would suggest sticking with that.
Some have suggested I should be more worried about being able to shift
packets than getting the LEDs working, but where's the fun in that? :)
quoted
quoted
I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.
Okay, back to my original wnr854t-support-v0a branch based on 4.6,
switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
add support, but there's no traffic in/out of any port. tcpdump on
the underlying ethernet port shows encapsulated broadcast traffic,
e.g. this ARP request from enp0:10.100.4.41:
00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
ethertype Unknown (0xc008), length 64:
0x0000: 0000 0806 0001 0800 0604 0001 1aff 0ffe ................
0x0010: 1022 0a64 0429 0000 0000 0000 0a64 0437 .".d.).......d.7
0x0020: 0000 0000 0000 0000 0000 0000 0000 0000 ................
0x0030: 0000 ..
...but no unicast traffic.
Uh, that does not look like EDSA tagging. Expect an ethertype of
0xdada. Also, if you get the latest tcpdump sources, it knows how to
decode the additional EDSA header which is added.
Okay. Frames sent from the port are EDSA-tagged (which isn't exactly
surprising), but I'm yet to see the switch receive 0xdada frames. Even
with the net-next branch which uses DSA_TAG_PROTO_EDSA for all chip types.
However, the ethertype is reflecting the port:-
lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:
My other one of these routers, running OpenWRT / Linux 3.3.8, shows the
same ethertypes, which suggests that the switch is still in DSA tagging
mode. I'll poke around further and see what I find.
quoted
quoted
Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx.
The reg, stats, and atu would be interesting.
Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
LEDs, cherry-picked the above commit. Pushed the result if it's
useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
net-next.
Yes, the debug code is a real pain. Something i'm working on in the
background, get something generic which is acceptable for mainline.
So as you say, no unicast traffic to/from the CPU port. The 18
sw_in_filtered also look suspicious.
Yes, I've also noticed this, but not got anywhere in finding out what
filtered means---is it a set of rules the PHY applies, if so where do they
come from?
+ port@3 {
+ reg = <3>;
+ label = "cpu";
+ ethernet = <ð>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
You don't need a fixed-link here. The cpu port is automatically
configured fixed at the highest speed the port will do.
However,
ð {
status = "okay";
- ethernet-port@0 {
- speed = <1000>;
- duplex = <1>;
- };
};
here you do need the fixed link, otherwise it thinks there is a PHY
connected and tried to do auto-negotiation. That will never work.
Andrew
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+ model = "Netgear WNR854-t";
+ compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+ "marvell,orion5x";
+
+ memory {
+ reg = <0x00000000 0x2000000>; /* 32 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ linux,stdout-path = &uart0;
There should only be at most 1 kconfig entry for all orion5x DT based
platforms.
Even though it needs arch/arm/mach-orion5x/board-wnr854t.c to init the
PCI? orion5x currently has other board _DT options, I presumed for this
reason.
quoted
+ bool "Netgear WNR854T (Flattened Device Tree)"
+ help
+ Say 'Y' here if you want your kernel to support the
+ Netgear WNR854T platform.
+
config MACH_WNR854T
bool "Netgear WNR854T"
help
--
Jamie Lentin
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On Tuesday, July 19, 2016 10:40:16 AM CEST Jamie Lentin wrote:
On Mon, 18 Jul 2016, Arnd Bergmann wrote:
quoted
On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
quoted
On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
quoted
I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.
Definitely not impossible to implement, but the driver doesn't work
as-is.
Ok.
Unfortunately this isn't something I can test as the PCIe port on the SoC
doesn't go anywhere in my case.
As I said, this wouldn't be a problem: we should consider the PCI and PCIe
ports on this chip as completely separate anyway, so we can work on
the drivers independently.
quoted
quoted
quoted
We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).
MBus windows are needed. See:
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
ORION5X_PCI_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
ORION_MBUS_PCI_MEM_ATTR,
ORION5X_PCI_MEM_PHYS_BASE,
ORION5X_PCI_MEM_SIZE);
in orion5x_setup_wins().
Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.
quoted
Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.
Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.
Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c.
Although I'd presume that it too would need late_initcall() or somesuch
mechanism to probe PCI once the GPIO controller is available.
Deferred probing should be fine once the driver is migrated from
pci_common_init() to registering the host bridge directly.
Arnd
On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
quoted
On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
quoted
I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.
Definitely not impossible to implement, but the driver doesn't work
as-is.
Ok.
Unfortunately this isn't something I can test as the PCIe port on the SoC
doesn't go anywhere in my case.
quoted
quoted
We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).
MBus windows are needed. See:
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
ORION5X_PCI_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
ORION_MBUS_PCI_MEM_ATTR,
ORION5X_PCI_MEM_PHYS_BASE,
ORION5X_PCI_MEM_SIZE);
in orion5x_setup_wins().
Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.
quoted
Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.
Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.
Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c.
Although I'd presume that it too would need late_initcall() or somesuch
mechanism to probe PCI once the GPIO controller is available.
I was also hoping that we could get to the point where pci_common_init()
is only used for legacy machines without DT and without multiplatform,
it seems I missed a couple of users here.
Arnd
However, the ethertype is reflecting the port:-
lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:
My other one of these routers, running OpenWRT / Linux 3.3.8, shows
the same ethertypes, which suggests that the switch is still in DSA
tagging mode. I'll poke around further and see what I find.
O.K. With this wrong, nothing is going to work.
I will check that the 6131 actually supports EDSA!
Andrew
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-07-19 14:16:50
[Reducing the Cc: list a bit to networking people]
Okay. Frames sent from the port are EDSA-tagged (which isn't exactly
surprising), but I'm yet to see the switch receive 0xdada frames.
Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all
chip types.
However, the ethertype is reflecting the port:-
lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:
O.K, we broke it :-(
The 6185 does not support EDSA, only DSA.
Vivien, this is going to cause us problems. We need two different
dsa_switch_driver structures, one for EDSA capable devices, and one
for those which are not.
Or we do something more radical, like add a driver callback to return
the tagging protocol, rather than hard code it in the structure? We
can then use a capability flag.
Andrew
From: Vivien Didelot <hidden> Date: 2016-07-19 15:04:50
Hi Andrew,
Andrew Lunn [off-list ref] writes:
[Reducing the Cc: list a bit to networking people]
quoted
Okay. Frames sent from the port are EDSA-tagged (which isn't exactly
surprising), but I'm yet to see the switch receive 0xdada frames.
Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all
chip types.
However, the ethertype is reflecting the port:-
lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:
O.K, we broke it :-(
The 6185 does not support EDSA, only DSA.
I'm wondering if EDSA could be simulated on 6185 (only) with the
CoreTagType register (0x19) and DoubleTag bit in Port Control (0x04)...
Or we do something more radical, like add a driver callback to return
the tagging protocol, rather than hard code it in the structure? We
can then use a capability flag.
The driver callback is the way to go. The supported tag format is
identifiable via the register layout. 6352 and newer have a 2-bit
FrameMode in Port Control (0x04), while 6185 has a single DSA_Tag bit.
A new switch operation can return the tag protocol enum, or an exposed
xmit/recv pair from net/dsa/tag_*.c, which must be used by the CPU.
Note: 88E6060 (which is likely to be supported by mv88e6xxx) has the
same issue and requires this, since it uses the Trailer tagging format.
Thanks,
Vivien