On Sun, 2014-06-01 at 00:55 +0000, fugang.duan@freescale.com wrote:

From: Eric Dumazet <redacted> Data: Saturday, May 31, 2014 12:22 AM

quoted

How cpu handles misaligned 32bit accesses ?

You mean use extra descriptor for misaligned bytes ? Or attach the misaligned bytes to header descriptor ?

I meant, maybe you could not force alignment of the IP/TCP headers on a
4byte boundary, but using +2 bytes offset

This way, frames would be 4-bytes aligned from the Etnernet Header.

So I connect to APPLE MAC book to test again, test result (applied the patches to our internal kernel 3.10.31):
High mem disable: tx bandwidth 942Mbps, cpu loading is 65%.
High mem enable: tx bandwidth 930Mbps, cpu loading is 100%. 
=> I don't know why kernel highmem config enable cause so much performance drop ???

For your above suggestion "using one descriptor per MSS, instead of two":
Yes, for imx6dl soc, we just do it like this.  For imx6sx soc FEC that support byte alignment,  so it also use one descriptor per MSS.

Thanks for your suggestion and response. Do you know why highmem cause much performance drop for SW TSO ?

Check NETIF_F_HIGHDMA : your driver might be able to advertise its
support.

Check your copies, because you might then need kmap()

For an example, read efx_skb_copy_bits_to_pio() in
drivers/net/ethernet/sfc/tx.c