Thread (28 messages) 28 messages, 6 authors, 2014-06-01

RE: [PATCH v1 4/6] net: fec: Increase buffer descriptor entry number

From: fugang.duan@freescale.com <hidden>
Date: 2014-05-30 15:46:51

From: Eric Dumazet <redacted> Data: Friday, May 30, 2014 11:41 PM
To: Duan Fugang-B38611
Cc: ezequiel.garcia@free-electrons.com; David Laight; Li Frank-B20596;
davem@davemloft.net; netdev@vger.kernel.org; shawn.guo@linaro.org;
bhutchings@solarflare.com; stephen@networkplumber.org
Subject: RE: [PATCH v1 4/6] net: fec: Increase buffer descriptor entry
number

On Fri, 2014-05-30 at 15:08 +0000, fugang.duan@freescale.com wrote:
quoted
If frag page data is not match the alignment for ethernet DMA controller,
there need three descriptor for one MSS:
quoted
One descriptor for headers, one for the first non-align bytes copied
from frag page, one for the rest of frag page.
quoted
You could avoid the 2nd descriptor, by copying the unaligned part of the
payload into first descriptor (containing headers : about 66 bytes or so
you have room, if not, increase the 128 bytes room to 192 bytes)
quoted
So one frame may cost descriptor number is: 3 x 45
May... but in general it would be closer of 2 * 45
Good idea!
quoted
So the descriptors slots set to 512 is not big, just is reasonable. Do
you think ?

I believe it is fine : that is about 5 64KB TSO packets.
Thanks,
Andy
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help