From: fugang.duan@freescale.com

quoted

64KB TSO packet, with MSS=1460 -> 44 segments  (44*1460 = 64240) with
MSS=1448 (TCP timestamps) -> 45 segments  (45*1448 = 65160)

This software TSO emulation uses at least 2 descriptors per MSS

one descriptor to hold the headers (ethernet + ip + tcp) one descriptor
(or two) to hold the payload for this MSS

Thanks for Eric's detail explain.

If frag page data is not match the alignment for ethernet DMA controller,
there need three descriptor for one MSS:
One descriptor for headers, one for the first non-align bytes copied from
frag page, one for the rest of frag page.

So one frame may cost descriptor number is: 3 x 45

No - that is 45 frames, typically needing 3 ring entries each.

And I will add interrupt coalescing support for tx and rx, which also cost some more descriptors.

So the descriptors slots set to 512 is not big, just is reasonable. Do you think ?

Software TSO generates lots of separate ethernet frames, there is no
absolute requirement to be able to put all of them into the tx ring at once.

The required size for the tx ring is much more likely to be related
to any interrupt mitigation that delays the refilling of ring entries.
512 sounds like a lot of tx ring entries.

The receive ring doesn't need to allow for fragments - your driver
is in control of allocating the buffers.
I didn't understand why you've based the number of rx ring entries
on PAGE_SIZE - IIRC that might be 64k, or even larger.
I'd have expected 128 or 256 rx ring entries to be typical, but
how many are needed is a separate issue.
If the system can keep up with the maximum ethernet data rate
I'd expect that a smaller number would be fine.
If it can't keep up you'll lose packets anyway.
Aggressive power saving (with wake on LAN) might need more.

	David