Thread (21 messages) 21 messages, 6 authors, 2002-09-19

Re: Info: NAPI performance at "low" loads

From: Alan Cox <hidden>
Date: 2002-09-18 21:06:44
Also in: lkml

On Wed, 2002-09-18 at 21:46, David S. Miller wrote:
   From: Alan Cox [off-list ref]
   Date: 18 Sep 2002 21:43:09 +0100
   
   The inb timing depends on the PCI bus. If you want proof set a Matrox
   G400 into no pci retry mode, run a large X load at it and time some inbs
   you should be able to get to about 100 milliseconds for an inb to
   execute
   
Matrox isn't using inb/outb instructions to IO space, it is being
accessed by X using MEM space which is done using normal load and
store instructions on x86 after the card is mmap()'d into user space.
It doesnt matter what XFree86 is doing. Thats just to load the PCI bus
and jam it up to prove the point. It'll change your inb timing
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