Re: [PATCH v18 09/13] cxl: Update CXL Endpoint AER handler
From: Jonathan Cameron <jic23@kernel.org>
Date: 2026-07-20 23:29:20
Also in:
linux-acpi, linux-cxl, linux-doc, linux-pci, lkml
On Fri, 17 Jul 2026 17:27:02 -0500 Terry Bowman [off-list ref] wrote:
Rename cxl_error_detected() to cxl_pci_error_detected() and rename the struct pci_error_handlers instance to cxl_pci_error_handlers to avoid shadowing the struct type tag. Document the unconditional CXL RAS read policy: on a dead link, readl() returns 0xFFFFFFFF which is interpreted as UCE bits set and triggers a panic. If RAS registers are not mapped the read is skipped and the frozen/perm_failure switch cases defer to AER recovery for devices without active CXL.mem traffic. Signed-off-by: Terry Bowman <redacted>
A couple of trivial things inline. Reviewed-by: Jonathan Cameron <redacted>
quoted hunk ↗ jump to hunk
drivers/cxl/core/ras.c | 24 +++++++++++++++--------- drivers/cxl/cxlpci.h | 8 ++++---- drivers/cxl/pci.c | 12 ++++++------ 3 files changed, 25 insertions(+), 19 deletions(-)diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 6f4a3c1b0bb85..d5dc2c22565da 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c@@ -328,10 +328,8 @@ bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem return true; } - -
This white space removal should be in patch 7 I think.
quoted hunk ↗ jump to hunk
-pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev); bool ue = false;@@ -349,10 +347,18 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, } /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. + * The CXL RAS read is unconditional regardless of channel
Keep the 80 char wrap for comments. Also local style is single space after . (I'm terrible at not following style on that stuff but do as I say not as I do!)
+ * state. Any uncorrectable error bit set in the CXL RAS + * status register triggers a panic because CXL.mem cache + * coherency is already lost; continuing risks silent data + * corruption across interleaved HDM regions. + * + * On a dead link readl() returns 0xFFFFFFFF which sets all + * UCE bits and also triggers the panic - this is intentional. + * If RAS registers are not mapped the read is skipped, the + * panic is not reached, and the frozen/perm_failure switch + * cases below handle AER recovery for devices without active + * CXL.mem traffic.
Now this comment I like. Good and clear and explaining the non obvious decision.
*/ ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL));
quoted hunk ↗ jump to hunk
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 5c21db36073fe..6cf1db7b85020 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c@@ -1000,18 +1000,18 @@ static void cxl_reset_done(struct pci_dev *pdev) } } -static const struct pci_error_handlers cxl_error_handlers = { - .error_detected = cxl_error_detected, - .slot_reset = cxl_slot_reset, - .resume = cxl_error_resume, - .reset_done = cxl_reset_done, +static const struct pci_error_handlers cxl_pci_error_handlers = { + .error_detected = cxl_pci_error_detected, + .slot_reset = cxl_slot_reset, + .resume = cxl_error_resume, + .reset_done = cxl_reset_done,
Do we need the re-indent? Nice to make it more obvious what didn't change.
};