Thread (30 messages) 30 messages, 4 authors, 2021-03-18

Re: Errant readings on LM81 with T2080 SoC

From: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Date: 2021-03-12 00:20:39
Also in: linux-hwmon, linux-i2c, lkml

On 12/03/21 1:07 pm, Guenter Roeck wrote:
On 3/11/21 3:47 PM, Chris Packham wrote:
quoted
On 12/03/21 10:34 am, Guenter Roeck wrote:
quoted
On 3/11/21 1:17 PM, Chris Packham wrote:
quoted
On 11/03/21 9:18 pm, Wolfram Sang wrote:
quoted
quoted
Bummer. What is really weird is that you see clock stretching under
CPU load. Normally clock stretching is triggered by the device, not
by the host.
One example: Some hosts need an interrupt per byte to know if they
should send ACK or NACK. If that interrupt is delayed, they stretch the
clock.
It feels like something like that is happening. Looking at the T2080
Reference manual there is an interesting timing diagram (Figure 14-2 if
someone feels like looking it up). It shows SCL low between the ACK for
the address and the data byte. I think if we're delayed in sending the
next byte we could violate Ttimeout or Tlow:mext from the SMBUS spec.
I think that really leaves you only two options that I can see:
Rework the driver to handle critical actions (such as setting TXAK,
and everything else that might result in clock stretching) in the
interrupt handler, or rework the driver to handle everything in
a high priority kernel thread.
One thing I've found that does seem to avoid the problem is to disable
preemption, use polling and replace the schedule() in i2c_wait() with
udelay(50). That's kind of like the kernel thread option.
It is kind of hackish, though, especially since it makes the "loaded system"
situation even worse by adding even more active wait loops.
No -ish about it :). But it might put out one fire for me while I'm 
looking at doing some kind of interrupt driven state machine.
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