Re: Errant readings on LM81 with T2080 SoC
From: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Date: 2021-03-11 21:18:36
Also in:
linux-hwmon, linux-i2c, lkml
From: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Date: 2021-03-11 21:18:36
Also in:
linux-hwmon, linux-i2c, lkml
On 11/03/21 9:18 pm, Wolfram Sang wrote:
quoted
Bummer. What is really weird is that you see clock stretching under CPU load. Normally clock stretching is triggered by the device, not by the host.One example: Some hosts need an interrupt per byte to know if they should send ACK or NACK. If that interrupt is delayed, they stretch the clock.
It feels like something like that is happening. Looking at the T2080 Reference manual there is an interesting timing diagram (Figure 14-2 if someone feels like looking it up). It shows SCL low between the ACK for the address and the data byte. I think if we're delayed in sending the next byte we could violate Ttimeout or Tlow:mext from the SMBUS spec.