Re: [PATCH 1/3] powerpc/mm/radix: Update pte update sequence for pte clear case

On Thu, 2017-02-09 at 08:28 +0530, Aneesh Kumar K.V wrote:

In the kernel we do follow the below sequence in different code paths.
pte =3D ptep_get_clear(ptep)
....
set_pte_at(ptep, pte)
=20
We do that for mremap, autonuma protection update and softdirty clearing.=

 This

implies our optimization to skip a tlb flush when clearing a pte update i=

s

not valid, because for DD1 system that followup set_pte_at will be done w=

itout

doing the required tlbflush. Fix that by always doing the dd1 style pte u=

pdate

irrespective of new_pte value. In a later patch we will optimize the
application
exit case.
=20
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Aneesh Kumar K.V <redacted>

Tested-by: Michael Neuling <redacted>

t

mm_struct *mm,
=C2=A0		=C2=A0* new value of pte
=C2=A0		=C2=A0*/
=C2=A0		new_pte =3D (old_pte | set) & ~clr;
-		/*
-		=C2=A0* If we are trying to clear the pte, we can skip
-		=C2=A0* the below sequence and batch the tlb flush. The
-		=C2=A0* tlb flush batching is done by mmu gather code
-		=C2=A0*/
-		if (new_pte) {
-			asm volatile("ptesync" : : : "memory");
-			radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);
+		asm volatile("ptesync" : : : "memory");
+		radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);
+		if (new_pte)
=C2=A0			__radix_pte_update(ptep, 0, new_pte);
-		}
=C2=A0	} else
=C2=A0		old_pte =3D __radix_pte_update(ptep, clr, set);
=C2=A0	asm volatile("ptesync" : : : "memory");