Re: [v3,11/41] mips: reuse asm-generic/barrier.h

On Tue, Jan 12, 2016 at 12:45:14PM -0800, Leonid Yegoshin wrote:

quoted

The issue I have with the SYNC description in the text above is that it
describes the single CPU (program order) and the dual-CPU (confusingly
named global order) cases, but then doesn't generalise any further. That
means we can't sensibly reason about transitivity properties when a third
agent is involved. For example, the WRC+sync+addr test:


P0:
Wx = 1

P1:
Rx == 1
SYNC
Wy = 1

P2:
Ry == 1
<address dep>
Rx = 0


I can't find anything to forbid that, given the text. The main problem
is having the SYNC on P1 affect the write by P0.

As I understand that test, the visibility of P0: W[x] = 1 is identical to P1
and P2 here. If P1 got X before SYNC and write to Y after SYNC then
instruction source register dependency tracking in P2 prevents a speculative
load of X before P2 obtains Y from the same place as P0/P1 and calculate
address of X. If some load of X in P2 happens before address dependency
calculation it's result is discarded.

I don't think the address dependency is enough on its own. By that
reasoning, the following variant (WRC+addr+addr) would work too:


P0:
Wx = 1

P1:
Rx == 1
<address dep>
Wy = 1

P2:
Ry == 1
<address dep>
Rx = 0


So are you saying that this is also forbidden?
Imagine that P0 and P1 are two threads that share a store buffer. What
then?

Yes, you can't find that in MIPS SYNC instruction description, it is more
likely in CM (Coherence Manager) area. I just pointed our arch team member
responsible for documents and he will think how to explain that.

I tried grepping the linked documents for "coherence manager" but couldn't
find anything. Is the description you refer to available anywhere?

Will