Thread (17 messages) 17 messages, 4 authors, 2013-01-31

Re: [PATCH 3/5] KVM: PPC: e500: Remove E.PT category from VCPUs

From: Alexander Graf <hidden>
Date: 2013-01-31 13:27:20
Also in: kvm

On 30.01.2013, at 14:29, Mihai Caraman wrote:
Embedded.Page Table (E.PT) category in VMs requires indirect tlb =
entries
emulation which is not supported yet. Configure TLBnCFG to remove E.PT
category from VCPUs.
=20
Signed-off-by: Mihai Caraman <redacted>
Please do this in a separate function that you call from these =
locations. That way the code is self-documenting on what it actually =
does.

Also add a comment to this one function that removes E.PT related bits =
from TLBCFG that our _guest_ mmu emulation currently doesn't handle =
E.PT.


Alex
quoted hunk ↗ jump to hunk
---
arch/powerpc/kvm/e500_mmu.c |   10 ++++++----
1 files changed, 6 insertions(+), 4 deletions(-)
=20
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index 129299a..9a1f7b7 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -692,12 +692,14 @@ int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu =
*vcpu,
	vcpu_e500->gtlb_offset[0] =3D 0;
	vcpu_e500->gtlb_offset[1] =3D params.tlb_sizes[0];
=20
-	vcpu->arch.tlbcfg[0] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+	vcpu->arch.tlbcfg[0] &=3D
+			      ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC | =
TLBnCFG_IND);
	if (params.tlb_sizes[0] <=3D 2048)
		vcpu->arch.tlbcfg[0] |=3D params.tlb_sizes[0];
	vcpu->arch.tlbcfg[0] |=3D params.tlb_ways[0] << =
TLBnCFG_ASSOC_SHIFT;
=20
-	vcpu->arch.tlbcfg[1] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+	vcpu->arch.tlbcfg[1] &=3D
+			      ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC | =
TLBnCFG_IND);
	vcpu->arch.tlbcfg[1] |=3D params.tlb_sizes[1];
	vcpu->arch.tlbcfg[1] |=3D params.tlb_ways[1] << =
TLBnCFG_ASSOC_SHIFT;
quoted hunk ↗ jump to hunk
=20
@@ -783,13 +785,13 @@ int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 =
*vcpu_e500)
=20
	/* Init TLB configuration register */
	vcpu->arch.tlbcfg[0] =3D mfspr(SPRN_TLB0CFG) &
-			     ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+			     ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC | =
TLBnCFG_IND);
	vcpu->arch.tlbcfg[0] |=3D vcpu_e500->gtlb_params[0].entries;
	vcpu->arch.tlbcfg[0] |=3D
		vcpu_e500->gtlb_params[0].ways << TLBnCFG_ASSOC_SHIFT;
=20
	vcpu->arch.tlbcfg[1] =3D mfspr(SPRN_TLB1CFG) &
-			     ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+			     ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC | =
TLBnCFG_IND);
	vcpu->arch.tlbcfg[1] |=3D vcpu_e500->gtlb_params[1].entries;
	vcpu->arch.tlbcfg[1] |=3D
		vcpu_e500->gtlb_params[1].ways << TLBnCFG_ASSOC_SHIFT;
--=20
1.7.4.1
=20
=20
--
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