On Wed, 2012-08-15 at 12:29 -0500, Scott Wood wrote:
quoted
---
arch/powerpc/kernel/pci-common.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 0f75bd5..2a09aa5 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -734,7 +734,7 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
hose->io_base_virt = ioremap(cpu_addr, size);
/* Expect trouble if pci_addr is not 0 */
- if (primary)
+ if (primary || !isa_io_base)
isa_io_base =
(unsigned long)hose->io_base_virt;
#endif /* CONFIG_PPC32 */
Didn't I already point out that this has problems when the primary bus
is not the first to be probed? If your answer is that you fix that in a
later patch, that breaks bisectability.
Is it though ? ie, we will override it with the real primary in the
above test, so it will only very temporarily be set to the "wrong" bus
no ? IE, the test will still trip on the actual "primary" if there's
one.
Cheers,
Ben.