Stephen Rothwell [off-list ref] writes:

Hi Aneesh,

On Mon,  9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V" [off-list ref] wrote:

quoted

diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 660b8bb..308e29d 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c

@@ -39,22 +39,33 @@
 
 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
 
-static inline void __tlbie(unsigned long va, int psize, int ssize)
+static inline void __tlbie(unsigned long vpn, int psize, int ssize)
 {
+	unsigned long va;
 	unsigned int penc;
 
+	/*
+	 * We need 14 to 65 bits of va for a tlibe of 4K page
+	 * With vpn we ignore the lower VPN_SHIFT bits already.
+	 * And top two bits are already ignored because we can
+	 * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
+	 * of 12.
+	 */
+	BUG_ON((77 - 65) > VPN_SHIFT);

BUILD_BUG_ON() ?

Yes. I also found a bug there. It should be updated as below

	BUILD_BUG_ON(VPN_SHIFT > (77 - 65));

We want to make sure we are not ignoring bits above 65th bit. 

quoted

-static inline void __tlbiel(unsigned long va, int psize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
 {
+	unsigned long va;
 	unsigned int penc;
 
+	BUG_ON((77 - 65) > VPN_SHIFT);

BUILD_BUG_ON() ?

-aneesh