On Nov 29, 2011, at 3:48 PM, Scott Wood wrote:

On 11/29/2011 03:40 PM, Artem Bityutskiy wrote:

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On Thu, 2011-11-24 at 08:24 -0600, Kumar Gala wrote:

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On Nov 22, 2011, at 9:41 PM, Kumar Gala wrote:
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On Oct 31, 2011, at 4:38 AM, [off-list ref] =

[off-list ref] wrote:

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From: Liu Shuo <redacted>
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Integrated Flash Controller supports various flashes like NOR, =

NAND

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and other devices using NOR, NAND and GPCM Machine available on =

it.

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IFC supports four chip selects.
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Signed-off-by: Dipen Dudhat <redacted>
Signed-off-by: Scott Wood <redacted>
Signed-off-by: Li Yang <redacted>
Signed-off-by: Liu Shuo <redacted>
---
arch/powerpc/Kconfig               |    4 +
arch/powerpc/include/asm/fsl_ifc.h |  834 =

++++++++++++++++++++++++++++++++++++

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arch/powerpc/sysdev/Makefile       |    1 +
arch/powerpc/sysdev/fsl_ifc.c      |  322 ++++++++++++++
4 files changed, 1161 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_ifc.h
create mode 100644 arch/powerpc/sysdev/fsl_ifc.c

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Guys,
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How are we handling this patchset since it touches =

drivers/mtd/nand?

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I do not see it touching MTD from the diffstat above. I am a little =

bit

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confused why a flash controller is added to
arch/powerpc/sysdev/fsl_ifc.c ?

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It's really a bus controller, with NOR, NAND, and general-purpose =

modes

settable per chipselect.  The actual NAND driver goes in
drivers/mtd/nand, and is apparently in a separate patch (probably due =

to

separate maintenance domains).
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It's the same situation as arch/powerpc/sysdev/fsl_lbc.c versus
drivers/mtd/nand/fsl_elbc_nand.c and drivers/mtd/nand/fsl_upm.c.
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-Scott

As Scott said, I was more asking about the 2nd patch in the sequence =
which did touch MTD.  Since that one is dependent on this patch, =
wondering how we wanted to handle them.

- k