=20
The PPC440X currently uses 256M TLB entries to pin the=20
lowmem. When we go for a relocatable kernel we have to :
=20
1) Restrict the kernel load address to be 256M aligned
=20
OR
=20
2) Use 16M TLB(the next possible TLB page size supported)=20
entries till the first
256M and then use the 256M TLB entries for the rest of lowmem.
What is wrong with:
3) Use 256M TLB entries with the lowest one including
addresses below the kernel base.
Clearly the kernel shouldn't be accessing the addresses
below its base address - but that is true of a lot of
address space mapped into the kernel.
David