[PATCH] PowerPC 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
From: Valentine Barshak <hidden>
Date: 2008-03-06 14:05:28
Use dcri_clrset() for PCIe SDR0 read/modify/write access. Signed-off-by: Valentine Barshak <redacted> --- arch/powerpc/sysdev/ppc4xx_pci.c | 11 ++++------- 1 files changed, 4 insertions(+), 7 deletions(-) diff -pruN linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c
--- linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:39:46.000000000 +0300
+++ linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:52:02.000000000 +0300@@ -645,7 +645,7 @@ static int __init ppc440spe_pciex_core_i int time_out = 20; /* Set PLL clock receiver to LVPECL */ - mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28); + dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); /* Shouldn't we do all the calibration stuff etc... here ? */ if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +659,7 @@ static int __init ppc440spe_pciex_core_i } /* De-assert reset of PCIe PLL, wait for lock */ - mtdcri(SDR0, PESDR0_PLLLCT1, - mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24)); + dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); udelay(3); while (time_out) {
@@ -712,9 +711,8 @@ static int ppc440spe_pciex_init_port_hw( mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 0x35000000); } - val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET); mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - (val & ~(1 << 24 | 1 << 16)) | 1 << 12); + (1 << 24) | (1 << 16), 1 << 12); return 0; }
@@ -1042,8 +1040,7 @@ static int __init ppc4xx_pciex_port_init port->link = 0; } - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20); + dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); msleep(100); return 0;