Re: TLB Miss booting linux kernel on ppc 405

I'm no expert but....

I did configure my device with the DCR enabled and connected the PLBv46
DCR to the PPC.  In the TLB miss ISR I read the PLB registers and the
MCSR I *DID* notice that the PLB error registers were set.

I added some asm code to read MCSR (see Xilinx UG011.pdf, page 213) and
I also added the asm code to read the DCR of the PLB.  Sure enough, the
MCSR and PLB-DCR registers showed a DPLBError.

It's only a couple of asm statements:

mfspr   r30, 0x23c



Question to Xilinx experts:
What would cause the PLB to issue the DPLBError?????




<note to Xilinx>

Hey Xilinx guys!
Can you hack the gdb included with EDK such that it will recognize the
MCSR when gdb reads registers!

</note to Xilinx>

 


On Thu, 2008-02-21 at 11:04 -0700, David Baird wrote:

Hi Robert,

On Wed, Feb 20, 2008 at 2:24 PM, Robert Woodworth
[off-list ref] wrote:

quoted

 I'm under the suspicion that the PLB is issuing an error when switching
 to virtual mode and that there is either a timing/synthesis error or a
 fundamental error with the way the FPGA is getting synthesized with the
 PLB.

Can you offer a suggestion how I can check to see if the PLB is
issuing an error (a good application note for me to read or anything)?
 I was having a similar problem in virtual mode on one of my systems,
and I might be able to see also if I am having a problem with the PLB
bus.

-David