Hi Robert,
On Wed, Feb 20, 2008 at 2:24 PM, Robert Woodworth
[off-list ref] wrote:
I'm under the suspicion that the PLB is issuing an error when switching
to virtual mode and that there is either a timing/synthesis error or a
fundamental error with the way the FPGA is getting synthesized with the
PLB.
Can you offer a suggestion how I can check to see if the PLB is
issuing an error (a good application note for me to read or anything)?
I was having a similar problem in virtual mode on one of my systems,
and I might be able to see also if I am having a problem with the PLB
bus.
-David