Re: TLB Miss booting linux kernel on ppc 405

I tracked the kernel execution using step one instruction (si) on gdb
and matching the jumps with the System.map.
It is a Data TLB Miss and this is the register dump after the miss occurs:

    r1: 00502090
    r2: 0000000f
    r3: c00003c0
    r4: c0000000
    r5: 00000000
    r6: 00000000
    r7: 74747955
    r8: 4c302c39
    r9: 00000000
    pc: 00001100
    lr: 00000018

Now I'm checking the PPC cache configurations on XPS, because when
treating the DTLB Miss Exception a Machine Check Exception occurs when
it works with L1. Does this makes sense or am I confusing things?

Thanks,

On Feb 13, 2008 3:17 PM, David Baird [off-list ref] wrote:

On Feb 13, 2008 9:50 AM, Ricardo Ayres Severo [off-list ref] wrote:

quoted

Hi All,

I'm using kernel 2.6.24 and when it comes to line 826 on the file
arch/ppc/kernel/head_4xx.S it gives a TLB Miss.

arch/ppc/kernel/head_4xx.S
823 start_here:
824
825         /* ptr to current */
826         lis    r2,init_task@h
827         ori    r2,r2,init_task@l

I am just curious: how did you find that you have TLB miss on that
line?  Is it an Instruction TLB miss or a Data TLB miss?

Can you paste a dump of your registers (in XMD, rrd and srrd)?

I was having TLB misses awhile back due to some other problems, but
never had any on that line though.
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-- 
Ricardo Ayres Severo [off-list ref]