quoted

The erratum says nothing about any HW bugs with L3 cache flush. I just 
mentioned that the L3 cache flush operation described in MPC7450 
Reference manual is similar to the L2 using the L3 cache hardware 
flushing mechanism. For instance, it requires a complete L3 locking 
before flushing.

Then I think we should use that mechanism in the Linux kernel.
Anything else is waiting for bugs to bite.

I just figured out ... we actually already have all of that cache flush
code :-) I wrote most of it in fact. It's just that for some (bad)
reasons, it's somewhat hidden in arch/powerpc/platforms/powermac/cache.S

So I think best would be to take it from there and make it more
generic ...

Cheers,
Ben.