Segher Boessenkool wrote:

quoted

Note that 745x processors have L3 cache installed and may have the same
problem requiring similar code modifications to use L3 hardware flushing
mechanism.

What does the erratum say?

The erratum says nothing about any HW bugs with L3 cache flush. I just 
mentioned that the L3 cache flush operation described in MPC7450 
Reference manual is similar to the L2 using the L3 cache hardware 
flushing mechanism. For instance, it requires a complete L3 locking 
before flushing.

The L3 is a very different beast from the L2, IIRC it is
a pure victim cache so it cannot have this problem at all?

I'm not sure if it is a pure victim cache. I read the MPC7450 reference 
manual and see that the L3 cache operates similarly to the L2. The main 
difference between those caches is that L3 uses an external SRAM memory 
while L2 is a pure on-chip cache.

Vlad.

Segher