RE: fsl booke MM vs. SMP questions

On Mon, 2007-05-28 at 17:05 +0800, Liu Dave-r63238 wrote:

Ben,

quoted

You never "loose" IPIs in the sense that you always get at least 1
interrupt for N IPIs and it's up to software to make sure not to lose
any event. The linux kernel arch code usually handles that with a
synchronous IPI mecanism.

Due to the synchronous IPI mechanism for TLB invalidatation, it is
very time exhausting, there are interrupt overhead and wait time for
sync.

Yup, there is, though you can try to optimize it such that you only sync
the CPUs involved with the IPIs, which often are only few.

I also noticed that tlb invalidation on the PowerPC 750 SMP system
is using the IPI mechanism, that is because the 750 can not broadcast
tlb invalidation ops.

Do we support that in linux ?
 

If the broadcast tlbivax instruction is more effective than the IPI
mechanism?

Did you evaluate the performance with the two different ways?

Not really... it depends on bus traffic, plus the need to spinlock the
broadcast tlbivax as well, etc..

I'm not working on real HW at the moment. I don't know what the exact
characteristics of your target HW are...

Ben.