Re: fsl booke MM vs. SMP questions

On Tue, May 22, 2007 at 08:07:52AM +1000, Benjamin Herrenschmidt wrote:

quoted

quoted

The tlb miss handler does:

 - tlbbusy = 1
 - barrier (make sure the following read is in order vs. the previous
store to tlbbusy)
 - read linux PTE value
 - write it to the HW TLB

and write the linux PTE with referenced bit?

I've kept the reference bit rewrite out of that pseudo-code because I
was approaching a different issue but yes. The idea i have there is to
do break down the linux PTE operation that way:

	 1 - rX = read PTE value (normal load)
	 2 - if (!_PAGE_PRESENT)) -> out
 	 3 - rY = rX | _PAGE_ACCESSED
	 4 - if (rX != rY)
	 5 -   rZ = lwarx PTE value
	 6 -   if (rZ != rX)
	 7 -	stdcx. PTE, rZ (rewrite just read value to clear reserv)

Why do you want to clear the reservation here? 

Coming out of some code path with the reservation still held 
can only affect buggy code (someone doing st[dw]cx. before 
l[dw]arx) AFAIK.

	 8 - 	goto 1 (try again)
	 9 -   stdcx. PTE, rY
	10 -   if failed -> goto 1 (try again)
	11 - that's it ! 

In addition, I suppose performance can be improved by also dealing with
dirty bit right in the TLB refill if the access is a write and the page
is writeable rather than taking a double fault.

	Regards,
	Gabriel